Computer Architecture and Performance
Course Period:Now ~ 2008-03-18
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Course Intro
Course Plan
1. The Processor:Datapath and Control Building a Datapath
2. Single-Cycle processor and Multi-Cycle Processor and Exceptions
3. Enhancing Performance with Pipelining
(a) A Pipelined Datapath
(b) Pipeline Control
(c) Pipeline Hazards
(d) Data hazards and Forwarding
(e) Data hazards and Stalls
(f) Branch hazards
4. Exploiting Memory Hierarchy
(a) The Cache Memory System
(b) Measuring and Improving Cache Performance
(c) Virtual Memory
5. Storage, Networks, and Other Peripherals
(a) Disk Storage and Dependability Networks
(b) I/O Interface and Performance
Textbooks
Computer Organization and Design: The Hardware/Software Interface, 3rd ed.,
David Patterson and John Hennessy, 2005
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Course Outline
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Designing a Single-cycle Processor
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Designing a Multi-cycle Processor
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Pipeline Processing-1
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Pipeline Processing-2
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Ch07-Memory Hierarchy
Teacher / 林學儀